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? semiconductor components industries, llc, 2009 september, 2009 ? rev. 0 1 publication order number: NCP4201/s NCP4201 programmable multi-phase synchronous buck converter with pmbus the NCP4201 is an integrated power control ic with a pmbus interface. it combines a highly efficient, multi ? phase, synchronous buck switching regulator controller with a pmbus interface, which enables digital programming of key system parameters to optimize system performance and provide feedback to the system. it uses an internal 8 ? bit dac to read a voltage identification (vid) code directly from the processor, which is used to set the output voltage between 0.375 v and 1.6 v. this device uses a multi ? mode pwm architecture to drive the logic ? level outputs at a programmable switching frequency that can be optimized for vr size and efficiency. the NCP4201 can be programmed to provide 2 ? , 3 ? , or 4 ? phase operation, allowing for the construction of up to four complementary buck ? switching stages. the NCP4201 supports psi , which is a power save mode. the NCP4201 includes a pmbus interface which can be used to program system set points such as voltage offset, load ? line and phase balance and output voltage. key system performance data, such as cpu current, cpu voltage, and power and fault conditions can also be read back over the pmbus from the NCP4201. the NCP4201 is specified over the extended commercial temperature range of 0 c to +85 c and is available in a 40 lead qfn package. features ? selectable 2 ? , 3 ? , or 4 ? phase operation at up to 1.5 mhz per phase ? pmbus interface ? enables digital programmability of set points and read ? back of monitored values ? logic ? level pwm outputs for interface to external high power drivers ? fast ? enhanced pwm for excellent load transient performance ? active current balancing between all output phases ? built ? in power ? good/crowbar blanking supports on ? the ? fly (otf) vid code changes ? digitally programmable 0.375 v to 1.6 v output supports both vr11 and vr11.1 specifications ? programmable short ? circuit protection with programmable latchoff delay ? supports psi ? power saving mode during light loads applications ? desktop pc power supplies for vrm modules http://onsemi.com pin assignment device * package shipping ? ordering information NCP4201mnr2g qfn40 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. *the ?g? suffix indicates pb ? free package. marking diagram qfn40 6x6 case 488ar a = assembly location wl = wafer lot yyww = date code g = pb ? free package 40 1 NCP4201 awlyywwg 2 od1 1 vcc3 vcc 4 sda pwm2 9 sw3 28 10 imon sw4 27 iref 26 rt 25 3 pwm1 alert 5 scl pwm3 6 en pwm4 8 29 sw2 7 30 gnd sw1 fbrtn vid0 rampadj psi fb vid2 vid7 40 18 39 19 38 20 37 vid1 comp odn csref vid3 cssum vid4 ilimitfs vid6 cscomp vid5 top view pin 1 indicator 24 23 22 21 16 17 14 15 12 13 11 36 35 34 33 32 31 fault trdet pwrgd NCP4201
NCP4201 http://onsemi.com 2 figure 1. simplified block diagram vcc precision reference delay ? + gnd NCP4201 23 en 11 pwrgd 6 rampadj 17 rt 16 pwm2 pwm3 pwm4 sw3 sw2 sw1 csref 7 cscom p sw4 cssum 21 fb 18 pwm1 vid2 vid1 vid7 vid6 40 29 28 com fbrtn 15 vid dac current measurement and limit crowbar current limit + ? cmp + ? cmp + ? + ? cmp 31 current balancing circuit 2 / 3 / 4 ? phase driver logic en set reset reset reset reset 35 36 37 38 24 22 10 14 + ? oscillator ? + 25 32 34 33 9 iref vid0 od1 8 imon control control control digital config & value registers control adc control 30 13 alert 3 2 26 27 pmbus scl sda 5 4 boot voltage & soft start control fault ilimitfs 19 1 vcc3 overvoltage threshold ? + 850mv ? + + ? csref uvlo shutdown shunt regulator 3.3v regulator undervoltage threshold limit registers comparator status registers + ? cmp reset odn 39 psi 20 12 trdet ? + voltage threshold vid5 vid4 vid3
NCP4201 http://onsemi.com 3 figure 2. application circuit fbrtn comp fb csref cssum cscomp iref imon odn od1 vcc3 psi vid0 vid1 vid2 vid3 vid4 vid5 alert fault sda scl en gnd ilimfs rt rampadj pwm2 pwm3 pwm4 sw3 sw4 pwm1 NCP4201 pwrgd vid7 vcc vid6 trdet sw2 sw1 1 2 3 4 8 7 6 5 adp3121 bst in od vcc drvh sw pgnd drvl 2.2 18nf 4.7 f 150 nh 10 4.7 f 10nf 1 2 3 4 8 7 6 5 adp3121 bst in od vcc drvh sw pgnd drvl 2.2 18nf 4.7 f 150 nh 10 4.7 f 10nf 1 2 3 4 8 7 6 5 adp3121 bst in od vcc drvh sw pgnd drvl 2.2 18nf 4.7 f 150 nh 10 4.7 f 10nf 1 2 3 4 8 7 6 5 adp3121 bst in od vcc drvh sw pgnd drvl 2.2 18nf 4.7 f 150 nh 10 4.7 f 10nf 121k 1k 1k 1k 1k 220k power good psi vin 12v vcc core vcc core (rtn) vcc sense vss sense 1nf 4.99k 4.7 f 348k alert fault pmbus interface
NCP4201 http://onsemi.com 4 absolute maximum ratings parameter symbol value unit input voltage range (note 1) v in ? 0.3 to 6.0 v fbrtn v fbrtn ? 0.3 to 0.3 v pwm2 to pwm4, rampadj ? 0.3 to v in +0.3 v sw1 to sw4 ? 5 to +25 v sw1 to sw4 (< 200 ns) ? 10 to +25 v all other inputs and outputs ? 0.3 to v in + 0.3 v storage temperature range t stg ? 65 to +150 c operating ambient temperature range 0 to 85 c esd capability, human body model (note 2) esd hbm 2 kv esd capability, machine body model (note 2) esd mm 100 v lead temperature soldering re ? flow (smd styles only, pb ? free versions (note 3) t sld 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latchup current maximum rating: 150 ma per jedec standard: jesd78 3. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d. thermal characteristics parameter symbol value unit thermal characteristics; qfn, 6mm x 6mm (note 1) thermal resistance, junction ? to ? air (note 4) r ja 27 c/w 4. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. operating ranges (note 1) parameter symbol min max unit input voltage (note 5) v in 1.7 24 v output voltage (adjustable version only) (note 6) v out 0.375 1.8 v ambient temperature t a 0 85 c 5. minimum v in = 1.7 v or (v out + v do ), whichever is higher. 6. maximum limit for v out = v out(nom) ? 10%.
NCP4201 http://onsemi.com 5 pin function descriptions pin no mnemonic description 1 vcc3 3.3 v power supply output. a capacitor from this pin to ground provided decoupling for the interval 3.3 v ldo. 2 alert alert output. open drain output that asserts low when the vr exceeds a programmable limit. 3 fault fault output. open drain output that asserts low when a fault has occurred. the fault can be due to vr or current limit, crowbar, or undervoltage. the trip points are loaded into registers. 4 sda digital input/output. pmbus serial data bidirectional pin. requires pmbus pullup. 5 scl digital input. pmbus serial bus clock open drain input. requires pmbus pullup. 6 en power supply enable input. pulling this pin to gnd disables the pwm outputs and pulls the pwrgd output low. 7 gnd ground. all internal biasing and the logic output signals of the device are referenced to this ground. 8 imon analog filter output. a capacitor from this pin to ground sets the default current monitor filter frequency. the frequency can be modified using the serial interface. 9 iref current reference input. an external resistor from this pin to ground sets the reference current for i fb , i ilimitfs and i th(x) . 10 rt frequency setting resistor input. an external resistor connected between this pin and gnd sets the oscillator frequency of the device. 11 rampadj pwm ramp current input. an external resistor from the converter input voltage to this pin sets the internal pwm ramp. 12 trdet transient detect. 13 fbrtn feedback return. vid dac and error amplifier reference for remote sensing of the output voltage. 14 comp error amplifier output and compensation point. 15 fb feedback input. error amplifier input for remote sensing of the output voltage. an external resistor between this pin and the output voltage sets the no load offset point. 16 csref current sense reference voltage input. the voltage on this pin is used as the reference for the current sense amplifier and the power ? good and crowbar functions. this pin should be connected to the common point of the output inductors. 17 cssum current sense summing node. external resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 18 cscomp current sense compensation point. a resistor and capacitor from this pin to cssum determines the gain of the current sense amplifier and the positioning loop response time. 19 ilimitfs current sense and limit scaling pin. an external resistor from this pin to cscomp sets the internal current sensing signal for current limit and imon. this value can be overwritten using the pmbus interface. 20 odn output disable logic output for phases 2 ? 4. this pin is actively pulled low when the en input is low or when vcc is below its uvlo threshold to signal to the driver ic that the driver high ? side and low ? side outputs should go low. 21 od1 output disable logic output for phase one. this pin is actively pulled low when the en input is low or when vcc is below its uvlo threshold to signal to the driver ic that the driver high ? side and low ? side outputs should go low. 22 to 25 sw4 to sw1 current balance inputs. inputs for measuring the current level in each phase. the sw pins of unused phases should be left open. 26 to 29 pwm4 to pwm1 logic ? level pwm outputs. each output is connected to the input of an external mosfet driver such as the adp3121. connecting the pwm4, and pwm3 outputs to vcc causes that phase to turn off, allowing the NCP4201 to operate as a 2 ? phase controller. 30 vcc supply voltage for the device. 31 to 38 vid7 to vid0 voltage identification dac inputs. these eight pins are pulled down to gnd, providing a logic zero if left open. when in normal operation mode, the dac output programs the fb regulation voltage from 0.375 v to 1.6 v. 39 psi power save interface. system signal to select single phase option. 40 pwrgd power ? good output. open ? drain output that signals when the output voltage is outside of the proper operating range.
NCP4201 http://onsemi.com 6 electrical characteristics v in = 5.0 v, fbrtn = gnd for typical values t a = 0 c to 85 c, unless otherwise noted. (note 1 and 3). parameter symbol conditions min typ max unit reference current reference bias voltage v iref 1.75 1.8 1.9 v reference bias current i iref r iref = 121 k 16 a error amplifier output voltage range (note 1) v comp 0 4.4 v accuracy v fb relative to nominal dac output, referenced to fbrtn (note 2) ? 7.7 +7.7 mv v fb(boot) in startup 1.041 1.05 1.059 v load line positioning accuracy ? 77 ? 80 ? 83 mv load line range ? 350 0 mv load line attenuation 0 100 % differential non ? linearity ? 1.0 +1.0 lsb input bias current i fb i fb = i iref 14.2 16 17.7 a offset accuracy vr offset register = 1 11111, vid = 1.0 v vr offset register = 01 1111, vid = 1.0 v ? 193.75 193.75 mv fbrtn current i fbrtn 70 200 a output current i comp fb forced to v out ? 3% 500 a gain bandwidth product gbw (err) comp = fb 20 mhz slew rate comp = fb 25 v/ s boot voltage hold time t boot internal timer 2.0 ms vid inputs input low voltage v il(vid) vid(x) 0.3 v input high voltage v ih(vid) vid(x) 0.8 v input current i in(vid) ? 5.0 a vid transition delay time (note 1) vid code change to fb change 200 ns no cpu detection turn ? off delay time vid code change to pwm going low 5.0 s oscillator frequency range (note 1) f osc 0.25 6.0 mhz frequency variation f phase t a = 25 c, r t = 460k , 4 ? phase t a = 25 c, r t = 220k , 4 ? phase t a = 25 c, r t =120k , 4 ? phase 220 260 500 850 290 khz output voltage v rt r t = 500 k to gnd 1.93 2.03 2.13 v rampadj output voltage v rampadj rampadj ? fb, v fb = 1.0 v, i rampadj = ? 50 a ? 50 +50 mv rampadj input current range i rampadj 5.0 60 a current sense amplifier offset voltage v os(csa) cssum ? csref (note 3) ? 0.7 +0.7 mv input bias current, csref i bias(csref) csref = 1.0 v ? 20 +20 a input bias current, cssum i bias(cssum) csref = 1.0 v ? 10 +10 na gain bandwidth product gbw (csa) cssum = cscomp 10 mhz slew rate c cscomp = 10 pf 10 v/ s input common ? mode range cssum and csref 0 3.0 v output voltage range 0.05 3.0 v output current i cscomp 500 a current limit latchoff delay time internal timer 8.0 ms
NCP4201 http://onsemi.com 7 electrical characteristics v in = 5.0 v, fbrtn = gnd for typical values t a = 0 c to 85 c, unless otherwise noted. (note 1 and 3). parameter unit max typ min conditions symbol psi input low voltage 0.3 v input high voltage 0.8 v input current ? 5.0 a assertion timing fsw = 300 khz 3.3 s de ? assertion timing fsw = 300 khz 825 ns trdet output low voltage v ol i out = ? 6 ma 150 300 mv imon clamp voltage 1.0 1.15 v accuracy 10 x (csref ? cscomp)/r ilim ? 3.0 3.0 % output current 800 a offset ? 3.0 3.0 mv current limit comparator i lim bias current i lim csref ? cscomp)/rilim, (csref ? cscomp) = 150 mv, rilimc=7.5 k 20 a current limit threshold current i cl 4/3 x i iref 20 a current balance amplifier common ? mode range v sw(x)cm ? 600 +200 mv input resistance r sw(x) sw(x) = 0 v 14 18 21 k input current i sw(x) sw(x) = 0 v 8.0 12 28 a input current matching i sw(x) sw(x) = 0 v ? 6.0 +6.0 % phase balance adjustment range low phase bal registers = 00000 ? 25 % phase balance adjustment range high phase bal registers = 1 1111 +25 % delay timer internal timer delay time register = 011 2.0 ms timer range low delay time register = 000 0.5 ms timer range high delay time register = 111 4.0 ms soft ? start internal timer soft ? start slope register = 010 0.5 v/ms timer range low soft ? start slope register = 000 0.1 v/ms timer range high soft ? start slope register = 111 1.5 v/ms enable input input low voltage v il(en) 0.3 v input high voltage v ih(en) 0.8 v input current i in(en) ? 1.0 a delay time t delay(en) en > 0.8v , internal delay 2.0 ms odn / od1 outputs output low voltage v ol(od1 ) i od(sink) = ? 400 a 160 500 mv output high voltage v oh(odn/1 ) i od(source) = 400 a 4.0 5.0 v odn /od1 pulldown resistor 60 k
NCP4201 http://onsemi.com 8 electrical characteristics v in = 5.0 v, fbrtn = gnd for typical values t a = 0 c to 85 c, unless otherwise noted. (note 1 and 3). parameter unit max typ min conditions symbol power ? good comparator undervoltage threshold v pwrgd(uv) relative to nominal dac output ? 600 ? 500 ? 400 mv undervoltage adjustment range low pwrgd_lo register = 000 ? 500 mv undervoltage adjustment range high pwrgd_lo register = 111 ? 150 mv overvoltage threshold v pwrgd(ov) relative to dac output, pwrgd_hi = 00 200 300 400 mv overvoltage adjustment range low pwrgd_hi register = 11 150 mv overvoltage adjustment range high pwrgd_hi register = 00 300 mv output low voltage v ol(pwrgd) i pwrgd(sink) = ? 4 ma 150 300 mv power good delay time during soft ? start internal timer 2.0 ms vid code changing 100 250 s vid code static 200 ns crowbar trip point v crowbar relative to dac output, pwrgd_hi = 00 200 300 400 mv crowbar adjustment range pwrgd_hi register 150 300 mv crowbar reset point relative to fbrtn 250 300 350 mv crowbar delay time t crowbar overvoltage to pwm going low vid code changing 100 250 s vid code static 400 ns pwm outputs output low voltage i pwm(sink) = ? 400 a v ol(pwm) 160 500 mv output high voltage i pwm(source) = 400 a v oh(pwm) 4.0 5.0 v pmbus interface logic high input voltage v ih(sda, scl) 2.1 v logic input low voltage v il(sda, scl) 0.8 v hysteresis 500 mv sda output low voltage v ol i sda = ? 6 ma 0.4 v input current i ih ; i il ? 1.0 1.0 a input capacitance c scl, sda 5.0 pf clock frequency f scl 400 khz scl falling edge to sda valid time 1.0 s alert / fault outputs output low voltage v ol i out = ? 6 ma 0.4 v output high leakage current i oh v oh = 5.0 v 1.0 ua analog / digital converter adc input voltage range 0 2.0 v total unadjusted error (tue) 1.0 % differential non ? linearity (dnl) 8 bits 1.0 lsb conversion time, voltage channel averaging enabled (32 averages) 80 ms
NCP4201 http://onsemi.com 9 electrical characteristics v in = 5.0 v, fbrtn = gnd for typical values t a = 0 c to 85 c, unless otherwise noted. (note 1 and 3). parameter unit max typ min conditions symbol supply vcc (note 1) vcc 4.70 5.25 5.75 v dc supply current i vcc v system = 13.2 v, r shunt = 340 20 25 ma uvlo turn ? on current 6.5 11 ma uvlo threshold voltage v uvlo vcc rising 10 v uvlo turn ? off voltage vcc falling 4.1 v vcc3 output voltage vcc3 i vcc3 = 1 ma 3.0 3.3 3.6 v 1. refer to electrical characteristics and application information for safe operating area. 2. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 3. values based on design and/or characterization. figure 3. master clock frequency vs. rt typical characteristics 0 500 1000 1500 2000 2500 0 100 200 300 400 500 600 700 800 900 rt (k ) frequency (khz) pwm1
NCP4201 http://onsemi.com 10 test circuits figure 4. closed ? loop output voltage accuracy figure 5. current sense amplifier vos figure 6. positioning voltage alert rt rampadj trdet fbrtn comp fb csref cssum cscomp ilimitfs odn od1 pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 vcc3 pwrgd psi vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vcc NCP4201 8 bit vid code +1 f 100 nf +12 v 100 nf +1.25 v 20 k 1 k 121 k 10 k sda fault en sdl imon gnd iref cssum 18 cscomp 17 30 vcc csref 16 gnd 7 39 k 680 100 nf 1 k 1 v adp4201 v os = cscomp ? 1 v 40 12 v 680 30 vcc 10 k 1 v adp4201 12 v v fb = fb v = 80mv ? fb v = 0 mv + ? 15 comp 14 fb 19 csref 7 gnd vid dac 680 680 680 680
NCP4201 http://onsemi.com 11 description the NCP4201 is a 4 phase dc ? dc regulator with a pmbus interface. a typical application circuit is shown in figure 2. startup sequence the NCP4201 follows the startup sequence shown in figure 7. after both the en and uvlo conditions are met, a programmable internal timer goes through one delay cycle td1. this delay cycle is programmed using delay command, default delay = 2 ms, see table 2 for programmable values. the first six clock cycles of td2 are blanked from the pwm outputs and used for phase detection as explained in the following section. then the programmable internal soft ? start ramp is enabled (td2) and the output comes up to the boot voltage of 1.05 v. the boot hold time is also set by delay command. this second delay cycle is called td3. during td3 the processor vid pins settle to the required vid code. when td3 is over, the NCP4201 reads the vid inputs and soft ? starts either up or down to the final vid voltage (td4). after td4 has been completed and the pwrgd masking time (equal to vid otf masking) is finished, a third cycle of the internal timer sets the pwrgd blanking (td5). the internal delay and soft ? start times are programmable using the serial interface, the delay command and the soft ? start commands. figure 7. startup sequence td1 5.0 v supply vtt i/o (NCP4201 en) vcc_core vr ready (NCP4201 pwrgd) cpu vid inputs v boot v vid uvlo threshold 0.85 v td5 (1.05 v) vid invalid td4 td2 td3 vid valid 50 s internal delay timer an internal timer sets the delay times for the start up sequence, td1, td3 and td5. the default time is 2 msec, which can be changed using the pmbus interface. this timer is used for multiple delay timings (td1, td3 and td5) during the startup sequence. also, it is used for timing the current limit latchoff as explained in the current limit section. the current limit timer is set to 4 times the delay timer. the delay timer is programmed using bits <2:0> of the ton delay command (0xd4). the delay can be programmed between 0.5 msec and 4 msec. table 1 provides the programmable delay times. table 1. delay codes code delay (msec) 000 0.5 001 1 010 1.5 011 2 = default 100 2.5 101 3 110 3.5 111 4 soft ? start the soft ? start slope for the output voltage is set by an internal timer. the default value is 0.5 v/msec, which can be programmed through the pmbus interface. after td1 and the phase detection cycle have been completed, the ss time (td2 in figure 2) starts. the ss uses the internal vid dac to increase the output voltage in 6.25 mv steps up to the 1.05 v boot voltage. once the ss circuit has reached the boot voltage, the boot voltage delay time (td3) is started. the end of the boot voltage delay time signals the beginning of the second soft ? start time (td4). the ss voltage changes from the boot voltage to the programmed vid dac voltage (either higher or lower) using 6.25 mv steps. the soft ? start slew rate is programmed using bits <2:0> of the ton_rise (0xd5) command code. table 2 provides the soft ? start values. table 2. slew rate codes code slew rate (v/msec) 000 0.1 001 0.3 010 0.5 = default 011 0.7 100 0.9 101 1.1 110 1.3 111 1.5
NCP4201 http://onsemi.com 12 figure 8 shows typical startup waveforms for the NCP4201. figure 8. typical startup waveforms phase detection during startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the pwm outputs. normally, the NCP4201 operates as a 4 ? phase pwm controller. to operate as a 3 ? phase controller: connect pwm4 to v cc . to operate as a 2 ? phase controller: connect pwm3 and pwm4 to v cc . to operate as a single phase controller: connect pmw2, pwm3, and pwm4 to v cc . prior to soft ? start, while en is high the pwm4, pwm3 and pwm2 pins sink approximately 100 a each. an internal comparator checks each pin?s voltage vs. a threshold of 3.0 v. if the pin is tied to v cc , it is above the threshold. otherwise, an internal current sink pulls the pin to gnd, which is below the threshold. pwm1 is low during the phase detection interval that occurs during the first six clock cycles of td2. after this time, if the remaining pwm outputs are not pulled to v cc , the 100 a current sink is removed, and they function as normal pwm outputs. if they are pulled to v cc , the 100 a current source is removed, and the outputs are put into a high impedance state. the pwm outputs are logic ? level devices intended for driving fast response external gate drivers such as the adp3121. because each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one output can be on at the same time to allow overlapping phases. master clock frequency the clock frequency of the NCP4201 is set with an external resistor connected from the rt pin to ground. the frequency follows the graph in figure 3. to determine the frequency per phase, the clock is divided by the number of phases in use. if all phases are in use, divide by 4. if 2 phases are in use then divide by 2. output voltage differential sensing the NCP4201 combines differential sensing with a high accuracy vid dac and reference, and a low offset error amplifier. this maintains a worst ? case specification of 9 mv differential sensing error over its full operating output voltage and temperature range. the output voltage is sensed between the fb pin and fbr tn pin. fb is connected through a resistor, r b , to the regulation point, usually the remote sense pin of the microprocessor. fbrtn is connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 70 a to allow accurate remote sensing. the internal error amplifier compares the output of the dac to the fb pin to regulate the output voltage. output current sensing the NCP4201 provides a dedicated current sense amplifier (csa) to monitor the total output current for proper voltage positioning vs. load current, for the i mon output and for current limit detection. sensing the load current at the output gives the total real time current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low ? side mosfet. this amplifier can be configured in several ways, depending on the objectives of the system, as follows: ? output inductor dcr sensing without a thermistor for lower cost. ? output inductor dcr sensing with a thermistor for improved accuracy with inductor temperature tracking. ? sense resistors for highest accuracy measurements. the positive input of the csa is connected to the csref pin, which is connected to the average output voltage. the inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input cssum. the feedback resistor between cscomp and cssum sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. the gain of the amplifier is programmable by adjusting the feedback resistor. this difference signal is used internally to offset the vid dac for voltage positioning. this difference signal can be adjusted between 50% and 150% of the external value using the pmbus load ? line calibration (0xde) and load ? line set (0xdf) commands. the dif ference between csref and cscomp is used as a dif ferential input for the current limit comparator. to provide the best accuracy for sensing current, the csa is designed to have a low offset input voltage. also, the sensing gain is determined by external resistors to make it extremely accurate.
NCP4201 http://onsemi.com 13 the cpu current can also be monitored over the pmbus. the current limit and the load ? line can be adjusted from the circuit component values over the pmbus. current limit set ? point the current limit threshold on the NCP4201 is programmed by a resistor between the i limfs pin and the cscomp pin. the i limfs current, i ilimfs , is compared with an internal current reference of 20 a. if i ilimfs exceeds 20 a then the output current has exceeded the limit and the current limit protection is tripped. i ilimfs v ilimfs v cscomp r ilimfs (eq. 1) where v ilimfs = v csref v csref v cscomp r cs r ph r l i load (eq. 2) i ilimfs v csref v cscomp r ilimfs assuming that: r cs r ph r l 1m (eq. 3) i.e. the external circuit is set up for a 1 m load ? line then the r ilimfs is calculated as follows: i ilimfs 1m i load r ilimitfs (eq. 4) assuming we want a current limit of 150 a that means that i limfs must equal 20 a at that load. 20 a 1m 150 a r ilimitfs 7.5 k (eq. 5) solving this equation for r limitfs we get 7.5 k . the current limit threshold can be modified from the resistor programmed value by using the pmbus interface using bits <4:0> of the current limit threshold command (0xe2). the limit is programmable between 50% of the external limit and 146.7% of the external limit. the resolution is 3.3%. table 3 gives some examples codes. table 3. current limit code current limit (% of external limit) 0 0000 50% 0 0001 53.3% 1 0000 100% = default 1 0001 103.3% 1 1110 143.3% 1 1111 146.7% current limit, short ? circuit and latchoff protection if the current limit is reached and td5 has completed, an internal latchoff delay time will start, and the controller will shut down if the fault is not removed. this delay is four times longer than the delay time during the startup sequence. the current limit delay time only starts after td5 has completed. if there is a current limit during startup, the NCP4201 will go through td1 to td5 and then start the latchoff time. because the controller continues to cycle the phases during the latchoff delay time, if the short is removed before the timer is complete, the controller can return to normal operation. the latchoff function can be reset by either removing/ reapplying the supply voltage to the NCP4201, or by toggling the en pin low for a short time. during startup when the output voltage is below 200 mv, a secondary current limit is active. this is necessary because the voltage swing of cscomp cannot go below ground. this secondary current limit limits the internal comp voltage to the pwm comparators to 1.5 v. this limits the voltage drop across the low ? side mosfets through the current balance circuitry. typical overcurrent latchoff waveforms are shown in figure 9. figure 9. overcurrent latchoff waveforms an inherent per phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. this limit is based on the maximum normal mode comp voltage. output current monitor i mon is an analog output from the NCP4201 representing the total current being delivered to the load. it outputs an accurate current that is directly proportional to the current set by the i limfs resistor. i imon 10 i ilimfs (eq. 6) the current is then run through a parallel rc connected from the i mon pin to the fbrtn pin to generate an accurately scaled and filtered voltage as per the specification. the size of the resistor is used to set the i mon scaling. the scaling is set such that i mon = 900 mv at the tdc current of the processor. this means that the r imon resistor should be chosen as follows.
NCP4201 http://onsemi.com 14 from the current limit set ? point paragraph we know the following: i ilimfs 1m i load r limifs (eq. 7) i imon 10 1m i load r limfs for a 150 a current limit r limfs = 7.5 k . assuming the tdc = 135 a then v mon should equal 900 mv when i load = 135 a. when i load = 135 a, i mon equals: (eq. 8) i imon 10 1m 135 a 7.5 k 180 a v imon 900 mv 180 a r mon this gives a value of 5 k for r mon . if the tdc and ocp limit for the processor have to be changed the because the i limitfs resistor sets up both the current limit and also the current out of the i mon pin, as explained earlier. the i mon pin also includes an active clamp to limit the i mon voltage to 1.15 v max while maintaining accuracy at 900 mv full scale. active impedance control mode for controlling the dynamic output voltage droop as a function of output current, the csa gain and load ? line programming can be scaled to be equal to the droop impedance of the regulator times the output current. this droop voltage is then used to set the input control voltage to the system. the droop voltage is subtracted from the dac reference input voltage directly to tell the error amplifier where the output voltage should be. this allows enhanced feed forward response. load ? line setting the load ? line is programmable over the pmbus on the NCP4201. it is programmed using the load ? line calibration (0xde) and load ? line set (0xdf) commands. the load ? line can be adjusted between 0% and 100% of the external r csa . in this example r csa = 1 m r o needs to 0.8 m therefore programming the load ? line calibration + load ? line set register to give a combined percentage of 80% will set the r o to 0.8 m table 4. load ? line commands code load ? line (as a percentage of r csa ) 0 0000 0% 0 0001 3.226% 1 0000 51.6% = default 1 0001 53.3% 1 1110 96.7% 1 1111 100% current control mode and thermal balance the NCP4201 has individual inputs (sw1 to sw4) for each phase that are used for monitoring the per phase current. this information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. this current balance information is independent of the average output current information used for positioning. the magnitude of the internal ramp can be set to optimize the transient response of the system. it also monitors the supply voltage for feed ? forward control for changes in the supply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. the balance between the phases can be programmed using the pmbus phase bal sw(x) commands (0xe3 to 0xe6). this allows each phase to be adjusted if there is a dif ference in temperature due to layout and airflow considerations. the phase balance can be adjusted from a default gain of 5 (bits 4:0 = 10000). the minimum gain programmable is 3.75 (bits 4:0 = 00000) and the max gain is 6.1718 (bits 4:0 = 11111). voltage control mode a high gain, high bandwidth, voltage mode error amplifier is used for the voltage mode control loop. the control input voltage to the positive input is set via the vid logic according to the voltages listed in table 10. the vid code is set using the vid input pins or it can be programmed over the pmbus using the vout_command. by default, the NCP4201 outputs a voltage corresponding to the vid inputs. to output a voltage following the vout_command the user first needs to program the required vid code. then the vid_en bits need to be enabled. the following is the sequence: 1. program the required vid code to the vout_command code (0x21). 2. set the vid_en bit (bit 3) in the vr config 1 a (0xd2) and on the vr config 1b (0xd3). this voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with resistor r b and is used for sensing and controlling the output voltage at this point. a current source (equal to iref) from the fb pin flowing through r b is used for setting the no load offset voltage from the vid voltage. the no load voltage is negative with respect to the vid dac for intel cpu?s.
NCP4201 http://onsemi.com 15 the value of r b can be found using the following equation: r b v vid v onl i fb (eq. 9) an offset voltage can be added to the control voltage over the serial interface. this is done using bits <5:0> of the vout_trim (0xdb) and vout_cal (0xdc) commands. the max offset that can be applied is 193.75 mv (even if the sum of the offsets > 193.75 mv). the lsb size is 6.25 mv. a positive offset is applied when bit 5 = 0. a negative offset is applied when bit 5 = 1. table 5. offset codes vout_ trim code trim offset voltage vout_ cal code cal offset voltage total offset voltage 00 1000 50 mv 00 0010 12.5 mv 62.5 mv 10 0001 ? 6.25 mv 10 1110 ? 87.5 mv ? 93.75 mv 00 1111 93.75 mv 10 0001 ? 6.25 mv 87.5 mv dynamic vid the NCP4201 has the ability to respond to dynamically changing vid inputs while the controller is running. this allows the output voltage to change while the supply is running and supplying current to the load. this is commonly referred to as dynamic vid (dvid). a dvid can occur under either light or heavy load conditions. the processor signals the controller by changing the vid inputs (or by programming a new vout_command) in a single or multiple steps from the start code to the finish code. this change can be positive or negative. when a vid bit changes state, the NCP4201 detects the change and ignores the dac inputs for a minimum of 200 ns. this time prevents a false code due to logic skew while the vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar blanking functions for a minimum of 100 s to prevent a false pwrgd or crowbar event. each vid change resets the internal timer. if a vid off code is detected the NCP4201 will wait for 5 sec to ensure that the code is correct before initiating a shutdown of the controller. the NCP4201 also uses the ton_transition command code (0xd6) to limit the dvid slew rates. these can be encountered when the system does a large single vid step for power state changes, thus the dvid slew rate needs to be limited to prevent large inrush currents. the transition slew rate is programmed using bits <2:0> of the ton_transition (0xd6) command code. table 6 provides the soft ? start values. table 6. transition rate codes code transition rate (v/msec) 000 1 001 3 010 5 = default 011 7 100 9 101 11 110 13 111 15 enhanced transients mode the NCP4201 incorporates enhanced transient response for both load step up and load release. for load step up it senses the output of the error amp to determine if a load step up has occurred and then sequences on the appropriate number of phases to ramp up the output current. for load release, it also senses the output of the error amp and uses the load release information to trigger the trdet pin, which is then used to adjust the error amp feedback for optimal positioning. this is especially important during high frequency load steps. additional information is used during load transients to ensure proper sequencing and balancing of phases during high frequency load steps as well as minimizing the stress on components such as the input filter and mosfets. reference current the i ref pin is used to set an internal current reference. this reference current sets i fb . a resistor to ground programs the current based on the 1.8 v output. i ref 1.8 v r iref (eq. 10) typically, r iref is set to 121 k to program i ref = 15 a. (eq. 11) i fb i ref 15 a power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open ? drain output whose high level (when connected to a pullup resistor) indicates that the output voltage is within the nominal limits. the nominal limits specified in the specifications above based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range, if the vid dac inputs are in no cpu mode, or whenever the en pin is pulled low. pwrgd is blanked during a dvid event for a period of 100 s to prevent false signals during the time the output is changing.
NCP4201 http://onsemi.com 16 the pwrgd circuitry also incorporates an initial turn ? on delay time (td5). prior to the ss voltage reaching the programmed vid dac voltage and the pwrgd masking time finishing, the pwrgd pin is held low. once the ss circuit reaches the programmed dac voltage, the internal timer operates. the default range for the pwrgd comparator is +300 mv and ? 500 mv. however these values can be adjusted over the pmbus. the high limit is programmed using bits <1:0> of command code 0xe0 and the low limit is programmed using bits <2:0> of command code 0xe1. the following is a table of the programmable values. table 7. pwrgd high limits code pwrgd high limits 00 +300mv (default) 01 +250 mv 10 +200 mv 11 +150 mv table 8. pwrgd low limits code pwrgd low limits 000 ? 500mv (default) 001 ? 450 mv 010 ? 400 mv 011 ? 350 mv 100 ? 300 mv 101 ? 250 mv 110 ? 200 mv 111 ? 150 mv power state indicator the psi pin is an input used to determine the operating state of the load. if this input is pulled low, the load is in a low power state and the controller asserts the odn pin low, which can be used to disable phases and maintain better efficiency at lighter loads. the sequencing into and out of low power operation is maintained to minimize output deviations as well as providing full power load transients immediately after exiting a low power state. the user can program how many phases are enabled when psi is asserted. by default only phase 1 is enabled. the number of phases enabled can be changed over the pmbus. however extreme care should be taken to ensure that od1 is connected to all phases enabled during psi . the number of phases enabled during psi is programmed using bits 6 and 7 of the mfr config command (0xd1). table 9. # phases enabled during psi code pwrgd high limits 00 1 ? phase (default) 01 2 ? phases 10 1 ? phase 11 1 ? phase the actual phases enabled, depends upon how many phases are enabled for normal operation. for example if 4 phases are enabled normally and 2 during psi , then phase 1 and phase 3 will be enabled during psi . output crowbar as part of the protection for the load and output components of the supply, the pwm outputs are driven low (turning on the low ? side mosfets) when the output voltage exceeds the upper crowbar threshold. this crowbar action stops once the output voltage falls below the release threshold of approximately 300 mv. the value for the crowbar limit follows the programmable pwrgd high limit. turning on the low ? side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvoltage is due to a short in the high ? side mosfet, this action current limits the input supply, or blows its fuse protecting the microprocessor from being destroyed. output enable and uvlo for the NCP4201 to begin switching the input, supply current to the controller must be higher than the uvlo threshold and the en pin must be higher than its 0.8 v threshold. this initiates a system startup sequence. if either uvlo or en is less than their respective thresholds, the NCP4201 is disabled. this holds the pwm outputs at ground and forces pwrgd, odn and od1 signals low. in the application circuit (see figure 2), the od1 pin should be connected to the od inputs of the external drivers for the phases that are always on. the odn pin should be connected to the od inputs of the external drivers on the phases that are shut down during low power operation. grounding the driver od inputs disables the drivers such that both drvh and drvl are grounded. this feature is important in preventing the discharge of the output capacitors when the controller is shut off. if the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. voltage monitoring the NCP4201 can monitor the voltage on the en pin and reports this back in a register. the adc range for the voltage measurements is 0 v to 2.0 v. v oltages greater than 2.0 v can be monitored using a resistor divider network. voltage measurements are 10 bits wide. shunt resistor the NCP4201 uses a shunt to generate 5.0 v from the 12 v supply range. a trade ? off can be made between the power dissipated in the shunt resistor and the uvlo threshold. figure 10 shows the typical resistor value needed to realize certain uvlo voltages. it also gives the maximum power dissipated in the shunt resistor for these uvlo voltages.
NCP4201 http://onsemi.com 17 figure 10. typical shunt resistor value and power dissipation for different uvlo voltage rshunt pshunt 2 ? 0603 limit 2 ? 0805 limit 400 350 200 150 10 11 14 15 300 250 8 9 12 13 16 0.325 icc (uvlo) 0.3 0.275 0.25 0.225 0.2 0.175 the maximum power dissipated is calculated using equation: p max v in(max) v cc(min) 2 r shunt (eq. 12) where: v in(max) is the maximum voltage from the 12 v input supply (if the 12 v input supply is 12 v 5%, v in(max) = 12.6 v; if the 12 v input supply is 12 v 10%, v in(max) = 13.2 v). v cc(min) is the minimum v cc voltage of the NCP4201. this is specified as 4.75 v. r shunt is the shunt resistor value. the cecc standard specification for power rating in surface ? mount resistors is: 0603 = 0.1 w, 0805 = 0.125 w, 1206 = 0.25 w. pmbus interface control of the NCP4201 is carried out using the pmbus interface. the physical protocol for pmbus closely matches that of smbus. the NCP4201 is connected to this bus as a slave device, under the control of a master controller. data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low ? to ? high transition when the clock is high might be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as no acknowledge. the master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the NCP4201, write operations contain one, two or three bytes, and read operations contain one or two bytes. the command code or register address determines the number of bytes to be read or written, see the register map for more information. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed (i.e. command code), and then data can be written to that register or read from it. the first byte of a read or write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this write byte operation is shown in figure 12. the device address is sent over the bus, and then r/w is set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. 1. the read byte operation is shown in figure 13. first the command code needs to be written to the NCP4201 so that the required data is sent back. this is done by performing a write to the NCP4201 as before, but only the data byte containing the register address is sent, because no data is written to the register. a repeated start is then issued and a read operation is then performed consisting of the serial bus address; r/w bit set to 1, followed by the data byte read from the data register. 2. it is not possible to read or write a data byte from a data register without first writing to the address pointer register, even if the address pointer register is already at the correct value. 3. in addition to supporting the send byte, the NCP4201 also supports the read byte, write byte, read word and write word protocols. (see system management bus specifications rev. 2.0 and the pmbus specification rev 1.1 part i and part ii for more information.)
NCP4201 http://onsemi.com 18 figure 11. send byte 1919 0 0 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 scl sda start by master ack. by NCP4201 frame 1 serial bus address byte frame 2 command code ack. by NCP4201 stop by master figure 12. write byte 1919 0 0 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 scl sda start by master ack. by NCP4201 frame 1 serial bus address byte frame 2 command code frame 3 data byte scl (continued) sda (continued) ack. by NCP4201 ack. by NCP4201 stop by master 9 1 d7 d6 d5 d4 d3 d2 d1 d0 figure 13. read byte repeated start by master ack. by NCP4201 frame 1 serial bus address byte frame 2 data byte from NCP4201 no ack. by master stop b y master 1919 0 0 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 scl sda start by master ack. by NCP4201 frame 1 serial bus address byte frame 2 command code ack. by NCP4201 1919 0 0 0 1 1 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 scl sda write operations the pmbus specification defines several protocols for different types of read and writes operations. the ones used in the NCP4201 are discussed in this section. the following abbreviations are used in the diagrams: s?start p?stop r?read w?write a?acknowledge a ?no acknowledge the NCP4201 uses the following pmbus write protocols. send byte in this operation, the master device sends a single command byte to a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends.
NCP4201 http://onsemi.com 19 for the NCP4201, the send byte protocol is used to clear faults. this operation is shown in figure 14. figure 14. send byte command slave address command code a a w sp 246 5 3 1 if the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ack and carry out a single byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda and the transaction ends. the byte write operation is shown in figure 15. figure 15. single byte write to a register slave address command code data a a w sa 246 5 3 17 p 8 write word in this operation, the master device sends a command byte and two data bytes to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends the first data byte. 7. the slave asserts ack on sda. 8. the master sends the second data byte. 9. the slave asserts ack on sda. 10. the master asserts a stop condition on sda and the transaction ends. the word write operation is shown in figure 16. figure 16. single word write to a register slave address command code data (lsb) a a w sap 246 5 3 178 data (msb) a 10 9 block write in this operation, the master device sends a command byte and a byte count followed by the stated number of data bytes to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code 5. the slave asserts ack on sda 6. the master sends the byte count n 7. the slave asserts ack on sda 8. the master sends the first data byte 9. the slave asserts ack on sda 10. the master sends the second data byte. 11. the slave asserts ack on sda 12. the master sends the remainder of the data byes 13. the slave asserts an ack on sda after each data byte. 14. after the last data byte the master asserts a stop condition on sda figure 17. block write to a register slave address command code data byte 1 a a w s 246 5 3 178 9 byte count = n aa ... 10 data byte 2 a ... data byte n p a 11 12 13 14 read operations the NCP4201 uses the following pmbus read protocols. read byte in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserted ack on sda. 6. the master sends a repeated start condition on sda. 7. the master sends the 7 bit slave address followed by the read bit (high). 8. the slave asserts ack on sda. 9. the slave sends the data byte. 10. the master asserts no ack on sda. 11. the master asserts a stop condition on sda and the transaction ends. figure 18. single byte read from a register slave address command code data a a w sa 246 5 3 17 8 s slave address a r 10 9 11 p
NCP4201 http://onsemi.com 20 read word in this operation, the master device receives two data bytes from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserted ack on sda. 6. the master sends a repeated start condition on sda. 7. the master sends the 7 bit slave address followed by the read bit (high) 8. the slave asserts ack on sda. 9. the slave sends the first data byte (low data byte). 10. the master asserts ack on sda. 11. the slave sends the second data byte (high data byte). 12. the masters asserts a no ack on sda. 13. the master asserts a stop condition on sda and the transaction ends. figure 19. word read from a command code slave address command code data (lsb) a a w sa 246 5 3 178 s slave address a r 10 9 data (msb) ap 12 11 13 block read in this operation, the master device sends a command byte, the slave sends a byte count followed by the stated number of data bytes to the master device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a repeated start condition on sda. 5. the master sends the 7 ? bit slave address followed by the read bit (high). 6. the slave asserts ack on sda. 7. the slave sends the byte count n. 8. the master asserts ack on sda. 9. the slave sends the first data byte. 10. the master asserts ack on sda. 11. the slave sends the remainder of the data byes, the master asserts an ack on sda after each data byte. 12. after the last data byte the master asserts a no ack on sda. 13. the master asserts a stop condition on sda. figure 20. block write to a command coder slave address byte count = n a w s 246 5 3 17 s slave address a r 812 11 data byte n p a 13 a data byte 1 a ... 10 9 ... pmbus timeout the NCP4201 includes a pmbus timeout feature. if there is no pmbus activity for 35 ms, the NCP4201 assumes that the bus is locked and releases the bus. this prevents the device from locking or holding the pmbus expecting data. some pmbus controllers cannot handle the pmbus timeout feature, so it can be disabled. configuration register 1 (0xd1) bit 3 smb_to_en = 1; pmbus timeout enabled. bit 3 todis = 0; pmbus timeout disabled (default). virus protection to prevent rogue programs or viruses from accessing critical NCP4201 register settings, the lock bit can be set. setting bit 0 of the lock/reset sets the lock bit and locks critical registers. in this mode, certain registers can no longer be written to until the NCP4201 is powered down and powered up again. for more information on which registers are locked see the register map. table 10. vr11.1 and vr11 x vid codes for the NCP4201 output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 off 0 0 0 0 0 0 0 0 off 0 0 0 0 0 0 0 1 1.60000 0 0 0 0 0 0 1 0 1.59375 0 0 0 0 0 0 1 1 1.58750 0 0 0 0 0 1 0 0 1.58125 0 0 0 0 0 1 0 1 1.57500 0 0 0 0 0 1 1 0 1.56875 0 0 0 0 0 1 1 1 1.56250 0 0 0 0 1 0 0 0
NCP4201 http://onsemi.com 21 table 10. vr11.1 and vr11 x vid codes for the NCP4201 output vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 1.55625 0 0 0 0 1 0 0 1 1.55000 0 0 0 0 1 0 1 0 1.54375 0 0 0 0 1 0 1 1 1.53750 0 0 0 0 1 1 0 0 1.53125 0 0 0 0 1 1 0 1 1.52500 0 0 0 0 1 1 1 0 1.51875 0 0 0 0 1 1 1 1 1.51250 0 0 0 1 0 0 0 0 1.50625 0 0 0 1 0 0 0 1 1.50000 0 0 0 1 0 0 1 0 1.49375 0 0 0 1 0 0 1 1 1.48750 0 0 0 1 0 1 0 0 1.48125 0 0 0 1 0 1 0 1 1.47500 0 0 0 1 0 1 1 0 1.46875 0 0 0 1 0 1 1 1 1.46250 0 0 0 1 1 0 0 0 1.45625 0 0 0 1 1 0 0 1 1.45000 0 0 0 1 1 0 1 0 1.44375 0 0 0 1 1 0 1 1 1.43750 0 0 0 1 1 1 0 0 1.43125 0 0 0 1 1 1 0 1 1.42500 0 0 0 1 1 1 1 0 1.41875 0 0 0 1 1 1 1 1 1.41250 0 0 1 0 0 0 0 0 1.40625 0 0 1 0 0 0 0 1 1.40000 0 0 1 0 0 0 1 0 1.39375 0 0 1 0 0 0 1 1 1.38750 0 0 1 0 0 1 0 0 1.38125 0 0 1 0 0 1 0 1 1.37500 0 0 1 0 0 1 1 0 1.36875 0 0 1 0 0 1 1 1 1.36250 0 0 1 0 1 0 0 0 1.35625 0 0 1 0 1 0 0 1 1.35000 0 0 1 0 1 0 1 0 1.34375 0 0 1 0 1 0 1 1 1.33750 0 0 1 0 1 1 0 0 1.33125 0 0 1 0 1 1 0 1 1.32500 0 0 1 0 1 1 1 0 1.31875 0 0 1 0 1 1 1 1 1.31250 0 0 1 1 0 0 0 0 1.30625 0 0 1 1 0 0 0 1 1.30000 0 0 1 1 0 0 1 0 1.29375 0 0 1 1 0 0 1 1
NCP4201 http://onsemi.com 22 table 10. vr11.1 and vr11 x vid codes for the NCP4201 output vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 1.28750 0 0 1 1 0 1 0 0 1.28125 0 0 1 1 0 1 0 1 1.27500 0 0 1 1 0 1 1 0 1.26875 0 0 1 1 0 1 1 1 1.26250 0 0 1 1 1 0 0 0 1.25625 0 0 1 1 1 0 0 1 1.25000 0 0 1 1 1 0 1 0 1.24375 0 0 1 1 1 0 1 1 1.23750 0 0 1 1 1 1 0 0 1.23125 0 0 1 1 1 1 0 1 1.22500 0 0 1 1 1 1 1 0 1.21875 0 0 1 1 1 1 1 1 1.21250 0 1 0 0 0 0 0 0 1.20625 0 1 0 0 0 0 0 1 1.20000 0 1 0 0 0 0 1 0 1.19375 0 1 0 0 0 0 1 1 1.18750 0 1 0 0 0 1 0 0 1.18125 0 1 0 0 0 1 0 1 1.17500 0 1 0 0 0 1 1 0 1.16875 0 1 0 0 0 1 1 1 1.16250 0 1 0 0 1 0 0 0 1.15625 0 1 0 0 1 0 0 1 1.15000 0 1 0 0 1 0 1 0 1.14375 0 1 0 0 1 0 1 1 1.13750 0 1 0 0 1 1 0 0 1.13125 0 1 0 0 1 1 0 1 1.12500 0 1 0 0 1 1 1 0 1.11875 0 1 0 0 1 1 1 1 1.11250 0 1 0 1 0 0 0 0 1.10625 0 1 0 1 0 0 0 1 1.10000 0 1 0 1 0 0 1 0 1.09375 0 1 0 1 0 0 1 1 1.08750 0 1 0 1 0 1 0 0 1.08125 0 1 0 1 0 1 0 1 1.07500 0 1 0 1 0 1 1 0 1.06875 0 1 0 1 0 1 1 1 1.06250 0 1 0 1 1 0 0 0 1.05625 0 1 0 1 1 0 0 1 1.05000 0 1 0 1 1 0 1 0 1.04375 0 1 0 1 1 0 1 1 1.03750 0 1 0 1 1 1 0 0 1.03125 0 1 0 1 1 1 0 1 1.02500 0 1 0 1 1 1 1 0
NCP4201 http://onsemi.com 23 table 10. vr11.1 and vr11 x vid codes for the NCP4201 output vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 1.01875 0 1 0 1 1 1 1 1 1.01250 0 1 1 0 0 0 0 0 1.00625 0 1 1 0 0 0 0 1 1.00000 0 1 1 0 0 0 1 0 0.99375 0 1 1 0 0 0 1 1 0.98750 0 1 1 0 0 1 0 0 0.98125 0 1 1 0 0 1 0 1 0.97500 0 1 1 0 0 1 1 0 0.96875 0 1 1 0 0 1 1 1 0.96250 0 1 1 0 1 0 0 0 0.95625 0 1 1 0 1 0 0 1 0.95000 0 1 1 0 1 0 1 0 0.94375 0 1 1 0 1 0 1 1 0.93750 0 1 1 0 1 1 0 0 0.93125 0 1 1 0 1 1 0 1 0.92500 0 1 1 0 1 1 1 0 0.91875 0 1 1 0 1 1 1 1 0.91250 0 1 1 1 0 0 0 0 0.90625 0 1 1 1 0 0 0 1 0.90000 0 1 1 1 0 0 1 0 0.89375 0 1 1 1 0 0 1 1 0.88750 0 1 1 1 0 1 0 0 0.88125 0 1 1 1 0 1 0 1 0.87500 0 1 1 1 0 1 1 0 0.86875 0 1 1 1 0 1 1 1 0.86250 0 1 1 1 1 0 0 0 0.85625 0 1 1 1 1 0 0 1 0.85000 0 1 1 1 1 0 1 0 0.84375 0 1 1 1 1 0 1 1 0.83750 0 1 1 1 1 1 0 0 0.83125 0 1 1 1 1 1 0 1 0.82500 0 1 1 1 1 1 1 0 0.81875 0 1 1 1 1 1 1 1 0.81250 1 0 0 0 0 0 0 0 0.80625 1 0 0 0 0 0 0 1 0.80000 1 0 0 0 0 0 1 0 0.79375 1 0 0 0 0 0 1 1 0.78750 1 0 0 0 0 1 0 0 0.78125 1 0 0 0 0 1 0 1 0.77500 1 0 0 0 0 1 1 0 0.76875 1 0 0 0 0 1 1 1 0.76250 1 0 0 0 1 0 0 0 0.75625 1 0 0 0 1 0 0 1
NCP4201 http://onsemi.com 24 table 10. vr11.1 and vr11 x vid codes for the NCP4201 output vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 0.75000 1 0 0 0 1 0 1 0 0.74375 1 0 0 0 1 0 1 1 0.73750 1 0 0 0 1 1 0 0 0.73125 1 0 0 0 1 1 0 1 0.72500 1 0 0 0 1 1 1 0 0.71875 1 0 0 0 1 1 1 1 0.71250 1 0 0 1 0 0 0 0 0.70625 1 0 0 1 0 0 0 1 0.70000 1 0 0 1 0 0 1 0 0.69375 1 0 0 1 0 0 1 1 0.68750 1 0 0 1 0 1 0 0 0.68125 1 0 0 1 0 1 0 1 0.67500 1 0 0 1 0 1 1 0 0.66875 1 0 0 1 0 1 1 1 0.66250 1 0 0 1 1 0 0 0 0.65625 1 0 0 1 1 0 0 1 0.65000 1 0 0 1 1 0 1 0 0.64375 1 0 0 1 1 0 1 1 0.63750 1 0 0 1 1 1 0 0 0.63125 1 0 0 1 1 1 0 1 0.62500 1 0 0 1 1 1 1 0 0.61875 1 0 0 1 1 1 1 1 0.61250 1 0 1 0 0 0 0 0 0.60625 1 0 1 0 0 0 0 1 0.60000 1 0 1 0 0 0 1 0 0.59375 1 0 1 0 0 0 1 1 0.58750 1 0 1 0 0 1 0 0 0.58125 1 0 1 0 0 1 0 1 0.57500 1 0 1 0 0 1 1 0 0.56875 1 0 1 0 0 1 1 1 0.56250 1 0 1 0 1 0 0 0 0.55625 1 0 1 0 1 0 0 1 0.55000 1 0 1 0 1 0 1 0 0.54375 1 0 1 0 1 0 1 1 0.53750 1 0 1 0 1 1 0 0 0.53125 1 0 1 0 1 1 0 1 0.52500 1 0 1 0 1 1 1 0 0.51875 1 0 1 0 1 1 1 1 0.51250 1 0 1 1 0 0 0 0 0.50625 1 0 1 1 0 0 0 1 0.50000 1 0 1 1 0 0 1 0 off 1 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 1
NCP4201 http://onsemi.com 25 table 11. pmbus commands for the NCP4201 cmd code r/w default description # bytes comment 0x01 r/w 0x80 operation 1 00xx xxxx ? immediate off 01xx xxxx ? soft off 1000 xxxx ? on (slew rate set by soft ? start) ? default 1001 10xx ? margin low (act on fault) 1010 10xx ? margin high (act on fault) 0x02 r/w 0x17 on_off_config 1 configures how the controller is turned on and off. bit default comment 7:5 000 reserved for future use 4 1 this bit is read only. switching starts when commanded by the control pin and the operation command, as set in bits 3:0. 3 0 0: unit ignores operation commands over the pmbus 1: unit responds to operation command, powerup may also depend upon control input, as described in bit 2 2 1 0: unit ignores en pin 1: unit responds en pin, powerup may also depend upon the operation register, as described for bit 3 1 1 control pin polarity 0 = active low 1 = active high 0 1 this bit is read only. 1: means that when the controller is disabled it will either immediately turn off or soft off (as set in the operation command) 0x03 w na clear_faults 0 writing any value to this command code will clear all status bits immediately. the smbus alert is deasserted on this command. if the fault is still present the fault bit shall immediately be asserted again. 0x10 r/w 0x00 write protect 1 the write_protect command is used to control writing to the pmbus device. there is also a lock bit in the manufacture specific registers that once set will disable writes to all commands until the power to the NCP4201 is cycled. data byte comment 1000 0000 disables all writes except to the write_protect command 0100 0000 disables all writes except to the write_protect and operation commands 0010 0000 disables all writes except to the write_protect, operation, on_off_config and vout_command commands 0000 0000 enables writes to all commands 0001 0000 disables all writes except to write_protect, page and all mfr ? specific commands 0x19 r 0xb0 capability 1 this command allows the host to get some information on the pmbus device. bit default comment 7 1 pec (packet error checking is supported) 6:5 01 max supported bus speed is 400 khz 4 1 NCP4201 has an smbus alert pin and ara is supported 3:0 000 reserved for future use 0x20 r 0x20 vout_mode 1 the NCP4201 supports vid mode for programming the output voltage. 0x21 r/w 0x00 vout_command 2 sets the output voltage using vid. 0x25 r/w 0x0020 vout_margin_high 2 sets the output voltage when operation command is set to margin high. programmed in vid mode.
NCP4201 http://onsemi.com 26 cmd code comment # bytes description default r/w 0x26 r/w 0x00b2 vout_margin_low 2 sets the output voltage when operation command is set to margin low. programmed in vid mode. 0x38 r/w 0x0001 iout_cal_gain 2 sets the ratio of voltage sensed to current output. scale is linear and is expressed in 1/ 0x39 r/w 0x0000 iout_cal_offset 2 this offset is used to null out any offsets in the output current sensing circuitry. units are amps 0x4a r/w 0x0064 iout_oc_warn_limit 2 this sets the high current limit. once this limit is exceeded iout_oc_warn_limit bit is set in the status_iout register and an alert is generated. this limit is set in amps. 0x68 r/w 0x012c pout_op_fault_limit 2 this sets the output power over power fault limit. once exceeded bit 1 of the status i out command gets set and the fault output gets asserted (if not masked). 0x6a r/w 0x012c pout_op_warn limit 2 this sets the output power over power warn limit. once exceeded bit 0 of the status i out command gets set and the alert output gets asserted (if not masked) 0x78 r 0x00 status byte 1 bit name description 7 busy a fault was declared because the NCP4201 was busy and unable to respond. 6 off this bit is set whenever the NCP4201 is not switching. 5 vout_ov this bit gets set whenever the NCP4201 goes into ovp mode. 4 iout_oc this bit gets set whenever the NCP4201 latches off due to an overcurrent event. 3 res 2 res 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault has occurred which is not one of the above. 0x79 r 0x0000 status word 2 byte bit name description low 7 res low 6 off this bit is set whenever the NCP4201 is not switching. low 5 vout_ov this bit gets set whenever the NCP4201 goes into ovp mode. low 4 iout_oc this bit gets set whenever the NCP4201 latches off due to an overcurrent event. low 3 res low 2 res low 1 cml a communications, memory or logic fault has occurred. high 0 none of the above a fault has occurred which is not one of the above. high 7 v out this bit gets set whenever the measured output voltage goes outside its power good limits or an ovp event has taken place, i.e. any bit in status v out is set. high 6 i out /p out this bit gets set whenever the measured output current or power exceeds its warning limit or goes into ocp. i.e. any bit in status i out is set. high 5 res high 4 mfr a manufacturer specific warning or fault has occurred.
NCP4201 http://onsemi.com 27 cmd code comment # bytes description default r/w high 3 power_ good the power ? good signal is deasserted. same as power ? good in general status. high 2 res high 1 other a status bit in status other is asserted. high 0 res 0x7a r 0x00 status vout 1 bit name description 7 vout_ over voltage fault this bit gets set whenever ovp event takes place. 6 vout_ over voltage warning this bit gets set whenever the measured output voltage goes above its power ? good limit. 5 vout_ under voltage warning this bit gets set whenever the measured output voltage goes below its power ? good limit. 4 vout_ under voltage fault not applicable. 3 res 2 res 1 res 0 res 0x7b r 0x00 status iout 1 bit name description 7 i out overcurrent fault this bit gets set if the NCP4201 latches off due to an ocp event. 6 res 5 i out overcurrent warning this bit gets set if i out exceeds its programmed high warning limit. 4 res 3 res 2 res 1 p out over power warning this bit gets set if the measured p out exceeds the fault limit. 0 p out over power warning fault this bit gets set if the measured p out exceeds the warn limit. 0x7e r 0x00 status cml 1 bit desc name 7 supported invalid or unsupported command received. 6 supported invalid or unsupported data received. 5 supported pec failed. 4 not supported memory fault detected. 3 not supported processor fault detected. 2 not supported 1 supported a communication fault other than the ones listed has occurred. 0 not supported other memory or logic fault has occurred.
NCP4201 http://onsemi.com 28 cmd code comment # bytes description default r/w 0x80 r 0x00 status_alert 1 bit name description 7 res 6 res 5 res 4 res 3 res 2 v mon warn gets asserted when v mon exceeds it programmed warn limits. 1 v mon fault gets asserted when v mon exceeds it programmed fault limits. 0 res 0x88 r 0x00 2 0x8b r 0x00 read_vout 2 read ? back output voltage. voltage is read back in vid mode. 0x8c r 0x00 read_iout 2 read ? back output current. current is read back in linear mode (amps). 0x8d r 0x00 2 0x96 r 0x00 read_pout 2 read ? back output power, read back in linear mode in w?s. 0x99 r 0x4101 mfr_id 1 0x4101 0x9a r 0x0002 mfr_model 2 0x0002 0x9b r 0x0301 mfr_revision 1 0x0301 table 12. manufacturer specific command codes for the NCP4201 cmd code r/w default description # bytes comment 0xdo r/w 0x00 lock/reset 1 bit name description 1 reset resets all registers to their por value. has no effect if lock bit is set. 0 lock logic 1 locks all limit values to their current settings. once this bit is set, all lockable registers become read ? only and cannot be modified until the NCP4201 is powered down and powered up again. this prevents rogue programs such as viruses from modifying critical system limit settings. (lockable). 0xd1 r/w 0x07 mfr config 1 bit name description 7:6 psi these bits sets the number of phases turned on during psi . 00 = cl set for 1 phase (default) 01 = cl set for 2 phases 10 = cl set for 1 phase 11 = cl set for 1 phase 5 res 4 res 3 pmb_to_en pmbus timeout enable. when the pmb_to_en bit is set to 1, the pmbus timeout feature is enabled. in this state if, at any point during an pmbus transaction involving the NCP4201, activity ceases for more than 35 ms, the NCP4201 assumes the bus is locked and releases the bus. this allows the NCP4201 to be used with smbus controllers that cannot handle smbus timeouts. (lockable). 2 fault _en enable the fault pin, default = 1. 1 alert _en enable the alert pin. 0 enable_ monitor when the enable_monitor bit is set to 1, the NCP4201 starts conversions with the adc and monitors the voltages.
NCP4201 http://onsemi.com 29 cmd code comment # bytes description default r/w 0xd2 r/w 0x52 vr config. 1a 1 bit name description 6:4 phase enable bits 000 = phase 1 100 = phase 2 010 = phase 3 110 = phase 4 3 vid_en when the vid_en bit is set to 1, the vid code in the vout_command register sets the output voltage. when vid_en is set to 0, the output voltage follows the vid input pins. 2 loop_en when the loop_en bit is set to 1 in both registers, the control loop test function is enabled. this allows measurement of the control loop ac gain and phase response with appropriate instrumentation. the control loop signal insertion pin is i mon . the control loop output pin is comp. 1 clim_en when clim_en is set to 1, the current limit time out latchoff functions normally. when this bit is set to 0 in both registers, the current limit latchoff is disabled. in this state, the part can be in current limit indefinitely. 0 res 0xd3 r/w 0x52 vr config. 1b 1 this register is for security reasons. it has the same format as register 0xd2. bits need to be set in both registers for the function to take effect. 0xd4 r/w 0x03 to n d e l a y 1 this resister sets td1, td 3 and td5 delays for the soft ? start sequence. the current limit latchoff timer is 4 times the programmed delay time: 000 = 0.5 ms 001 = 1 ms 010 = 1.5 ms 011 = 2 ms = default 100 = 2.5 ms 101 = 3 ms 110 = 3.5 ms 111 = 4 ms 0xd5 r/w 0x02 to n r i s e 1 this register sets the soft ? start voltage slew rate, and hence td2 and td4, of the soft ? start sequence: 000 = 0.1 v/ms 001 = 0.3 v/ms 010 = 0.5 v/ms = default 011 = 0.7 v/ms 100 = 0.9 v/ms 101 = 1.1 v/ms 110 = 1.3 v/ms 111 = 1.5 v/ms 0xd6 r/w 0x01 ton transition 1 this register sets the slew rate during dynamic vid. 0xd8 r 0x00 en/vtt voltage 2 this is a 16 bit value that reports back the voltage on the vtt pin. voltage is reported using linear mode. 0xda r 0x00 vmon voltage 1 this is a 16 bit value that reports back the voltage measured between fb and fbrtn. voltage is reported using linear mode. 0xdb r/w 0x00 vout_trim 1 offset command code for v out , max 200 mv. 0xdc r/w 0x00 vout_cal 1 offset command code for v out , max 200 mv. 0xde r/w 0x10 load ? line calibration 1 this value sets the internal load ? line attenuation dac calibration value. the maximum load ? line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. this maximum load ? line can then be adjusted from 100% to 0% in 30 steps. each lsb represents a 3.226% change in the load ? line. 00000 = no load ? line 10000 = 51.6% of external load ? line 11111 = 100% of external load ? line
NCP4201 http://onsemi.com 30 cmd code comment # bytes description default r/w 0xdf r/w 0x00 load ? line set 1 this value sets the internal load ? line attenuation dac value. the maximum load ? line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. this maximum load ? line can then be adjusted from 100% to 0% in 30 steps. each lsb represents a 3.226% change in the load ? line. 00000 = no load ? line 10000 = 51.6% of external load ? line 11111 = 100% of external load ? line 0xe0 r/w 0x00 pwrgd hi threshold 1 this value sets the pwrgd hi threshold and the crowbar threshold: code = 00, pwrgd hi = 300 mv (default) code = 01, pwrgd hi = 250 mv code = 10, pwrgd hi = 200 mv code = 11, pwrgd hi = 150 mv 0xe1 r/w 0x00 pwrgd lo threshold 1 this value sets the pwrgd lo threshold: code = 000, pwrgd lo = ? 500 mv (default) code = 001, pwrgd lo = ? 450 mv code = 010, pwrgd lo = ? 400 mv code = 011, pwrgd lo = ? 350 mv code = 100, pwrgd lo = ? 300 mv code = 101, pwrgd lo = ? 250 mv code = 110, pwrgd lo = ? 200 mv code = 111, pwrgd lo = ? 150 mv 0xe2 r/w 0x10 current limit threshold 1 this value sets the internal current limit adjustment value. the default current limit is programmed using a resistor to ground on the limit pin. the value of this register adjusts this value by a percentage between 50% and 146.7%. each lsb represents a 3.33% change in the current limit threshold. 11111 = 146.7% of external current limit 10000 = 100% of external current limit (default) 00000 = 50% of external current limit 0xe3 r/w 0x10 phase bal sw1 1 these values adjust the gain of the internal phase balance amplifiers. the nominal gain is set to 5. these registers can adjust the gain by 25% from 3.75 to 6.1718. code = 00000, gain of 3.75 code = 10000, gain of 5 (default) code = 1 1111, gain of 6.1718 0xe4 r/w 0x10 phase bal sw2 1 these values adjust the gain of the internal phase balance amplifiers. the nominal gain is set to 5. these registers can adjust the gain by 25% from 3.75 to 6.1718. code = 00000, gain of 3.75 code = 10000, gain of 5 (default) code = 1 1111, gain of 6.1718 0xe5 r/w 0x10 phase bal sw3 1 these values adjust the gain of the internal phase balance amplifiers. the nominal gain is set to 5. these registers can adjust the gain by 25% from 3.75 to 6.1718. code = 00000, gain of 3.75 code = 10000, gain of 5 (default) code = 1 1111, gain of 6.1718 0xe6 r/w 0x10 phase bal sw4 1 these values adjust the gain of the internal phase balance amplifiers. the nominal gain is set to 5. these registers can adjust the gain by 25% from 3.75 to 6.1718. code = 00000, gain of 3.75 code = 10000, gain of 5 (default) code = 1 1111, gain of 6.1718 0xf5 r/w 0x0002 v mon fault limit 2 v mon fault limit 0xf6 r/w 0x0002 v mon warn limit 2 v mon warn limit 0xf9 r/w 0x00 mask alert 1 bit name description 7 mask v out masks any alert caused by bits in status v out register. 6 mask i out masks any alert caused by bits in status i out register. 5 res 4 res
NCP4201 http://onsemi.com 31 cmd code comment # bytes description default r/w 3 mask cml masks any alert caused by bits in status cml register. 2 v mon masks any alert caused by v mon exceeding its high or low limit. 1 res 0 mask p out masks any alert caused by p out exceeding its programmed limit. 0xfa r/w 0x00 mask fault 1 bit name description 7 mask v out masks any fault caused by bits in status v out register. 6 mask i out masks any fault caused by bits in status i out register. 5 res 4 res 3 mask cml masks any fault caused by bits in status cml register. 2 v mon masks any alert caused by v mon exceeding its high or low limit. 1 res 0 mask p out masks any fault caused by p out exceeding its programmed limit. 0xfb r 0x00 general status 1 bit name description 7 fault 6 alert 5 power_ good replaced by bit 3 of the status word command 4 rdy 0xfc r 0x00 phase status 1 bit name description 5 phase 4 this bit is set to 1 when phase 4 is enabled. 4 phase 3 this bit is set to 1 when phase 3 is enabled. 3 phase 2 this bit is set to 1 when phase 2 is enabled. 2 psi this bit is set to 1 when psi is asserted.
NCP4201 http://onsemi.com 32 package dimensions qfn40 6x6, 0.5p case 488ar ? 01 issue a seating 40x k 0.15 c (a3) a a1 d2 b 1 11 20 21 40 2x 2x e2 40x 10 30 40x l 40x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 4.00 4.20 e 6.00 bsc 4.20 e2 4.00 e 0.50 bsc l 0.30 0.50 k 0.20 ??? 36x plane dimensions: millimeters 0.50 pitch 4.20 0.30 4.20 40x 36x 0.65 40x 6.30 6.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP4201/s literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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